So what’s next for the XT/IDE project? Besides the few DPv1b and DPv2 boards left, effectively none of the boards are available. For the DPv2, many hobbyists will be unwilling to tackle SMT boards and being just over 100mm wide, it’s expensive to have made by (eg) Seeedstudio as a one-off.
Andrew Lynch periodically orders a short run of the ‘Mk.II’ XT/IDE board, although currently it looks that all stock is depleted. Other projects, such as the ‘JR-IDE’ controller for the PCJnr, are ongoing but again have no boards available to buy for an ordinary PC as of right now.
Dangerous Prototypes v2
One motivation behind the Dangerous Prototypes development with SMT was the possibility of a cost-effective short run of finished boards – professionally assembled with the CPLD and EEPROM programmed. In effect, the first new commercial 8-bit ISA card probably for at least 15 years 🙂
The problem is quantities, as to be viable it needs demand enough for 100 boards or more. Since there’s probably only been 100 of the original XT/IDE boards ever made, that just seems unlikely.
Separately, I wanted to re-work the DPv2 design to use a Compact Flash (CF) header instead of a 40-pin header. A quick survey of VC Forum members showed interest in CF, but only with a 40-pin header too.
Why Compact Flash?
DOS can only access about 8GB, which is way more than could ever be filled with XT class software, yet CF cards that size are currently about £10. And being solid-state, they have near zero command latency – look at the performance numbers side-by-side with the ST-412 in the ubiquitous PC/XT:
ST-412 C.F. Read (KB/s): 64 210 Write (KB/s): 62 110 Sector IOPS: 6 13
And don’t think CF cards top-out at 13 IOPS; that’s just a reflection of the file system processing speed with a 4.77MHz 8088. The same CF card on the same XT/IDE controller (with ‘chuck-mod’) in a Pentium-200 turns in over 1MB/s and 700 IOPS – compared to about 140 IOPS from a current SATA drive.
Why not SD or SDHC?
The great advantage of CF cards is that they have a ‘true-IDE’ mode, in which they behave like an IDE disk. This is why CF-to-IDE adapters are so simple; literally they are just a plug adapter with a couple of LEDs thrown in for good measure. So modifying the DPv2 for CF should be quite straightforward, whereas implementing an SD card controller would require a CPLD with much more capacity and some supporting hardware with it.
Against the Grain
So going completely against the survey, my card as it exists today has only a CF slot, mounted so the CF card is accessible through the expansion slot bracket (but not hot-pluggable). Originally based on the DPv2, there’s now little left in the design from it other than the CPLD choice (the Xilinx XC9572XL). By replacing the EEPROM with a flash chip and revising the logic design, it should be quite a bit cheaper than the DPv2.
But as ever, there’s a problem: it needs a custom ISA bracket. Laser cutting and punch-press are options, but only cost effective at 50 units+. But for prototyping, I’ve managed to get one made by a friend.
The first challenge is revising Pietja’s CPLD code for my board; since the CF header pinout is ‘muddled up’ compared to the IDE 40-pin header, it made sense to just adjust the CPLD pinout to match, rather than mess about with complex PCB trace routing. The Xilinx CPLD coding is developed through Xilinx ISE, which helpfully they provide for free (after registration).
The next problem is programming the SST39SFxxx flash chip. It’s byte-programmable but with a software data protection scheme (which prevents bad code elsewhere over-writing the contents) that isn’t supported by the XTIDE universal BIOS utility, flashing this card will be a two-step process: configuring and saving the ROM image with the xt-ide universal BIOS configuration utility, then flashing the card using my own simple flash utility.
The First Cut…
So the prototype board has been built, the bracket pressed, the flashing utility compiled. After quite a learning curve with ISE… it works!
So far I’ve only adjusted Pietja’s DPv2 CPLD code for it (changed the pinout and ROM decode), and this is the original XT/IDE design, but it’s a start. The next step is to generate CPLD code for my revised circuit design that I hope will get writes going as fast as reads do with the ‘chuck-mod’ – but that’s all a job for another day.
Interested in building one of these? All the parts can be sourced from Farnell, and the resources you need are right here – some notes on SMT soldering and the XT-CF wiki page through which you can find CPLD code, parts lists and the flashing utility. You’ll need some way to program the CPLD too (via the JTAG header).
I’ve got a few of these blank PCBs to give away, so leave your email address in a comment (won’t be visible to others) and I’ll send you one for nothing!Social tagging: XT-IDE