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  • *Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding) *Regardless of the chip used, the first 32KB only will be mapped into the PC address space
    7 KB (1,021 words) - 11:11, 21 April 2021
  • !Page Frame Base Address !!IO Port Base Address !Value (1,2) !!Base Address
    2 KB (307 words) - 11:11, 21 April 2021
  • !Base Address !!Sw1 !!Sw2 !!Sw3 !!Sw4 === Address Mappings ===
    5 KB (793 words) - 11:11, 21 April 2021
  • The ROM decoder matches the PC address bus against the configuration of appropriate DIP switches, providing an ass ...itself under the control of /MEMR and /MEMW and the low 14-bits of the PC address bus.
    13 KB (2,136 words) - 17:36, 17 August 2022
  • *Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding) *Fixed resource allocation - IO ports 300-31Fh, ROM 32KB at C800h
    3 KB (490 words) - 18:06, 17 August 2022
  • *Configurable ROM base address - C800h or D800h *Configurable IO Port base address - 300h or 320h (change require BIOS flash)
    8 KB (1,215 words) - 19:31, 12 July 2022
  • ...s that support EMS, this provides a way to install more than the 1MB total address capacity of the 8086 and 8088 processors. ...ich are programmed through IO ports. A jumper block enables the page frame IO port base addresses to configured to match the system requirements.
    4 KB (630 words) - 19:39, 12 July 2022
  • ...ge Settings" with the adapter is highlighted ([[IRQ|IRQ]], [[IO Address|IO Address]], [[DMA Channel|DMA Channel]], etc)
    3 KB (487 words) - 11:11, 21 April 2021
  • *8-bit Port-mapped IO *16-but Port-mapped IO (supported on most systems; provides a performance advantage with 8088 and
    9 KB (1,357 words) - 17:41, 17 August 2022
  • ...from a single host. The board also features user-selectable IRQ and memory address options, enabling multiple cards to be used in a single system. The board i *JP4 configures the IO port range used, between 300h and 370h (see table below). Roland default is
    5 KB (702 words) - 19:39, 12 July 2022
  • *Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding) *Fixed resource allocation - IO ports 300-31Fh, ROM 32KB at C800h
    5 KB (665 words) - 11:11, 21 April 2021
  • *Port-mapped IO *Memory-mapped IO
    14 KB (2,061 words) - 17:40, 17 August 2022
  • ...M image (or images) in any PC with an ISA slot. The DIP switches allow an address base selectable between 8000h and F800h and configuration as either 32KB or ...of the chip used, the first 32KB or 64KB (only) will be mapped into the PC address space
    7 KB (1,109 words) - 11:11, 21 April 2021
  • *Regardless of the chip used, the first 32KB only will be mapped into the PC address space *Base address configuration per [[#DIP Switch Settings|DIP Switch Settings]]
    10 KB (1,492 words) - 11:11, 21 April 2021
  • *DIP switches allow address base selectable between 8000h and F800h and configuration as either 32KB or ...lines'), data lines, and read/write command lines. For each bus cycle, the address lines are set first, and the values held. Then on the next cycle, the read
    8 KB (1,248 words) - 19:38, 12 July 2022
  • *Selectable BIOS address - C800h or D800h *Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
    7 KB (1,167 words) - 12:35, 18 August 2022
  • *Selectable BIOS address - C800h or D800h *Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding)
    12 KB (1,765 words) - 07:04, 19 August 2022
  • *Port-mapped IO; supports both 8- and 16-bit instructions (via partial address decoding) *Fixed resource allocation - IO ports 300-31Fh, ROM 32KB at C800h
    11 KB (1,681 words) - 11:11, 21 April 2021
  • *via IO ports 40-47h, for use with a suitable device driver; or *via IO ports C8-CFh, for use with the LS-DOS (and system ROM) built-in drivers.
    8 KB (1,279 words) - 19:40, 12 July 2022
  • *Card IO Port should be set in the BIOS to 300h or 320h, matching the configuration *The BIOS base address option (C800h or D800h) can be changed via JP1 without re-flashing the BIOS
    7 KB (1,174 words) - 11:11, 21 April 2021

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